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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. mos integrated circuit m m m m pd16879 monolithic quad h bridge driver circuit document no. s14188ej1v0ds00 (1st edition) date published july 2000 n cp(k) printed in japan data sheet 2000 the m pd16879 is a monolithic quad h bridge driver ic that employs a cmos control circuit and a mosfet output circuit. because it uses mosfets in its output stage, this driver ic consumes less power than conventional driver ics that use bipolar transistors. because the m pd16879 controls a motor by inputting serial data, its package has been shrunk and the number of pins reduced. as a result, the performance of the application set can be improved and the size of the set has been reduced. this ic employs a current-controlled 64-step micro step driving method that drives stepper motor with low vibration. the m pd16879 is a housed in a 38-pin shrink sop to contribute to the miniaturization of application set. this ic can simultaneously drive two stepper motors and is ideal for the mechanisms of camcorders. features four h bridge circuits employing power mos fets current-controlled 64-step micro step driving motor control by serial data (8 bits 13 bytes) pwm-frequency, output current and number of output pulse can be setting by serial data. 3-v power supply. minimum operating voltage: 2.7 v low consumption current. v dd pin current (operating mode) : 3 ma (max.) power save circuit bult in. v dd pin current (power save mode) : 100 m a (max.) f clk : off state v dd pin current (power save mode) : 300 m a (max.) f clk : 4.5 mhz input 38-pin shrink sop (7.62 mm (300)) ordering information part number package m pd16879gs-bgg 38-pin plastic shrink sop (7.62 mm (300))
data sheet s14188ej1v0ds00 2 m m m m pd16879 absolute maximum ratings (t a = +25c) when mounted on a glass epoxy board (100 mm 100 mm 1 mm, 15% copper foil) parameter symbol conditions rating unit v dd control part C0.5 to +6.0 v supply voltage v m output part C0.5 to +11.2 v input voltage v in C0.5 to v dd + 0.5 v reference voltage v ref external input 0.5 v i m(dc) dc 0.15 a/ch h bridge drive current i m(pulse) pw < 10 ms, duty < 5 % 0.3 a/ch power consumption p t 1.0 w peak junction temperature t ch(max) 150 c storage temperature t stg C55 ~ +150 c recommended operating range (t a = +25c) when mounted on a glass epoxy board (100 mm 100 mm 1 mm, 15% copper foil) parameter symbol conditions min. typ. max. unit v dd control part 2.7 5.5 v supply voltage v m output part 4.0 11 v input voltage v in 0v dd v reference voltage v ref external input 225 250 275 mv exp pin input voltage v expin v dd v exp pin input current i expin 100 m a i m(dc) dc - 0.1 +0.1 a/ch h bridge drive current i m(pulse) p w < 10 ms, duty < 5% - 0.2 +0.2 a/ch clock frequency (osc in )f clk c osc = 68 pf, v ref = 250 mv 3.9 4.5 6.0 mhz clock frequency amplitude v fclk 0.7 v dd v dd v serial clock frequency f sclk 5.0 mhz video sync signal width pw (vd) f clk = 4.5 mhz 250 ns latch signal wait time t (vd-latch) 400 ns sclk wait time t (sclk-latch) 400 ns sdata setup time t setup 80 ns sdata hold time t hold refer to fig. 1 80 ns reset signal pulse width t rst 100 m s operating temperautre t a - 10 85 c peak junction temperature t ch(max) 125 c
data sheet s14188ej1v0ds00 3 m m m m pd16879 electrical characteristics (unless otherwise specified, t a = 25 c, v dd = 3 v, v m = 5.4 v, f clk = 4.5 mhz, c osc = 68 pf, c fil = 1000 pf, v ref = 250 mv, evr = 100 mv (10000)) parameter symbol conditions min. typ. max. unit off state v m pin current i mo(reset) no load, reset period 1.0 m a operating state v dd pin current i dd output open 3.0 ma v dd pin current i dd(reset) reset period 100 m a i dd(ps)1 t clk = off 100 m a power save state v dd pin current i dd(ps)2 f clk = 4.5 mhz 300 m a high level input voltage v ih 0.7 v dd v low level input voltage v il 0.3 v dd v input hysteresis vosltage v h latch, sclk, sdata, v d , v d reset, osc in , v refsel 0.3 v v om a (h) v om b (h) 0.9 v dd v monitor output voltage 1 (extout a , b ) v om a (l) v om b (l) 4th byte - 0.3 0.1 v dd v v oexp(h) pull up (v dd )0.9 v dd v monitor output voltage 2 (exp 0,1 open drain) v oexp(l) i oexp = 100 m a0.1 v dd v high level input current i ih v in = v dd 1.0 m a low level input current i il v in = 0 - 1.0 m a reset pin high level input current i ih(rst) v rst = v dd 1.0 m a reset pin low level input current i il(rst) v rst = 0 - 1.0 m a h bridge on resistance r on i m = 100 ma, upper + lower 6.0 w chopping frequency note 1 f osc refer to table 1 (typ.) khz internal reference voltage v ref 225 250 275 mv v d delay time note 2 d t vd 250 ns sin wave peak output current (reference value) note 3 i m l = 15 mh/r = 70 w ( 1 khz) r s = 6.8 w , f osc = 72.58 khz evr = 220 mv (11100) 53 ma fil pin voltage note 4 v evr evr = 200 mv (11010) v ref = 250 mv external input 370 400 430 mv fil pin step voltage note 4 v evrstep minimum step 20 mv h bridge turn on time note 5 t onh 2.0 m s h bridge turn off time note 5 t offh i m = 100 ma 2.0 m s notes 1. when data are less than 7 (000111), pwm chopping doesnt do it, and output pulse doesnt occur. when data are beyong 49, pwm chopping frequency becomes a 225 khz fixation. 2. by osc in and v d sync circuit 3. fb pin is monitored. 4. fil pin is monitored. a voltage about twice that of the evr value is output to the fil pin. 5. 10% to 90% of the pulse peak value without filter capacitor (c fil )
data sheet s14188ej1v0ds00 4 m m m m pd16879 fig 1. delay time of serial data ignored because latch is at low level 104 clocks (8 bits 13 bytes) ignored because latch is at low level t (vd-latch) t (sclk-latch) t (sclk-latch) t (sclk-latch) t setup t hold 50% 50% 50% d1 d2 d3 latch sdata sclk latch sclk v d v d table 1. chopping frequency (3rd byte d5 to d0 bit data, f clk = 4.5 mhz) typical value input data d5 to d0 bit chopping frequency (khz) input data d5 to d0 bit chopping frequency (khz) 001000 35.71 011101 132.35 001001 40.18 011110 132.35 001010 45.00 011111 140.63 001011 50.00 100000 140.63 001100 53.57 100001 150.00 001101 59.21 100010 150.00 001110 62.50 100011 160.71 001111 68.18 100100 160.71 010000 72.58 100101 160.71 010001 77.59 100110 173.08 010010 80.36 100111 173.08 010011 86.54 101000 173.08 010100 90.00 101001 187.50 010101 93.75 101010 187.50 010110 97.83 101011 187.50 010111 102.27 101100 204.55 011000 107.14 101101 204.55 011001 112.50 101110 204.55 011010 118.42 101111 204.55 011011 118.42 110000 225.00 011100 125.00 note when data are less than 7 (000111), pwm chopping doesnt do it, and output pulse doesnt occur. when data are beyond 49, pwm chopping frequency becomes a 225 khz fixation.
data sheet s14188ej1v0ds00 5 m m m m pd16879 table 2. relation between rotation angle, phase current, and vector quantity (64-division micro step) (value of m pd16879 for reference) a phase current b phase current vector quantity step rotation angle ( q ) min. typ. max. min. typ. max. typ. q 00 - 0 -- 100 - 100 q 1 5.6 2.5 9.8 17.0 - 100 - 100.48 q 2 11.3 12.4 19.5 26.5 93.2 98.1 103 100 q 3 16.9 22.1 29.1 36.1 90.7 95.7 100.7 100.02 q 4 22.5 31.3 38.3 45.3 87.4 92.4 97.4 100.02 q 5 28.1 40.1 47.1 54.1 83.2 88.2 93.2 99.99 q 6 33.8 48.6 55.6 62.6 78.1 83.1 88.1 99.98 q 7 39.4 58.4 63.4 68.4 72.3 77.3 82.3 99.97 q 8 45 65.7 70.7 75.7 65.7 70.7 75.7 99.98 q 9 50.6 72.3 77.3 82.3 58.4 63.4 68.4 99.97 q 10 56.3 78.1 83.1 88.1 48.6 55.6 62.6 99.98 q 11 61.9 83.2 88.2 93.2 40.1 47.1 54.1 99.99 q 12 67.5 87.4 92.4 97.4 31.3 38.3 45.3 100.02 q 13 73.1 90.7 95.7 100.7 22.1 29.1 36.1 100.02 q 14 78.8 93.2 98.1 103 12.4 19.5 26.5 100 q 15 84.4 - 100 - 2.5 9.8 17.0 100.48 q 16 90 - 100 -- 0 - 100 remark these data do not indicate guaranteed values.
data sheet s14188ej1v0ds00 6 m m m m pd16879 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 lgnd c osc fil a fil b fil c fil d v ref v dd v m3 d 2 fb d d 1 v m4 c 2 fb c c 1 exp0 exp1 v refsel reset osc out osc in sclk sdata latch v d v d b 2 fb b b 1 v m2 a 2 fb a a 1 v m1 ext ext pgnd b a
data sheet s14188ej1v0ds00 7 m m m m pd16879 pin function package: 38-pin plastic shrink sop pin pin name pin function 1 lgnd control circuit gnd pin 2c osc chopping capacitor connection pin 3fil a a 1 ch filter capacitor connection pin 4fil b a 2 ch filter capacitor connection pin 5fil c b 1 ch filter capacitor connection pin 6fil d b 2 ch filter capacitor connection pin 7v ref reference voltage input pin (250 mv typ) note 1 8v dd control circuit supply voltage input pin 9v m3 output circuit supply voltage input pin 10 d 2 b 2 ch output pin 11 fb d b 2 ch sense resistor connection pin 12 d 1 b 2 ch output pin 13 v m4 output circuit supply voltage input pin 14 c 2 b 1 ch output pin 15 fb c b 1 ch sense resistor connection pin 16 c 1 b 1 ch ouptut pin 17 exp0 external extension pin (open drain) 18 exp1 external extension pin (open drain) 19 v refsel reference voltage select pin note 1 20 pgnd output circuit gnd pin 21 ext aa ch logic circuit monitor pin 22 ext bb ch logic circuit monitor pin 23 v m1 output circuit supply voltage input pin 24 a 1 a 1 ch output pin 25 fb a a 1 ch sense resistor connection pin 26 a 2 a 1 ch output pin 27 v m2 output circuit supply voltage input pin 28 b 1 a 2 ch output pin 29 fb b a 2 ch sense resistor connection pin 30 b 2 a 2 ch output pin 31 v d video sync signal input pin note 2 32 v d video sync signal input pin note 2 33 latch latch signal input pin 34 sdata serial data input pin 35 sclk serial clock input pin (4.5 mhz typ) 36 osc in original oscillation input pin (4.5 mhz typ) 37 osc out original oscillation output pin 38 reset reset signal input pin remark plural terminal (v m ) is not only 1 terminal and connect all terminals. notes 1. a standard voltage to use is chosen. v refsel : high level using external input v ref v refsel : low level using internal reference voltage (v ref pin fixed gnd level) 2. input the video sync singnal to v d pin or v d pin. a free terminal is to do the following treatment. when input v d : v d pin connect to v dd pin. when input v d : v d pin connect to gnd pin.
data sheet s14188ej1v0ds00 8 m m m m pd16879 i/o pin equivalent circuit pin name equivalent circuit pin name equivalent circuit v d v d latch sdata sclk osc in reset v refsel v dd pad v ref v dd pad v refsel internal 250 mv osc out ext a ext b v dd pad exp0 exp1 v dd pad fil a fil b fil c fil d v dd pad buffer a 1 , a 2 b 1 , b 2 c 1 , c 2 d 1 , d 2 v m parasitic diodes pad fb
data sheet s14188ej1v0ds00 9 m m m m pd16879 block diagram reset v dd v m1 v m2 v m3 v m4 c osc lgnd pgnd 1 20 38 8 23 27 9 13 2 osc in osc out v d v d sclk sdata latch exp0 exp1 v refsel v ref 36 37 32 31 35 34 33 17 18 19 7 1/n osc filter v m h bridge 1ch a + + + + + + + + filter v m filter v m filter v m h bridge 2ch a h bridge 1ch b h bridge 2ch b serial-pararelle decoder pulse generater current set current set b a extout selector vref select 250 mv b.g.r 2 ext ext a b 21 22 25 24 26 3 29 28 30 4 15 16 14 5 11 12 10 6 fb a a 1 a 2 fil a ext fb b b 1 b 2 fil b fb c c 1 c 2 fil c fb d d 1 d 2 fil d remark plural terminal (v m ) is not only 1 terminal and connect all terminals.
data sheet s14188ej1v0ds00 10 m m m m pd16879 example of standard connection cpu 100 k w 2 4.5 mhz typ. using internal reference serial-parallele decoder pulse generator extout selector 2 vref select 250 mv b.g.r 1/n osc current set current set a b regulator battery 4.0 v to 11 v motor 1 motor 2 filter filter filter filter h bridge 1ch h bridge 1ch h bridge 1ch h bridge 1ch a a b b reset 2.7 v to 5.5 v 68 pf v dd v m1 v m2 v m3 v m4 c osc 38 8 23 27 9 13 2 1 20 lgnd pgnd 6.8 w 2 1000 pf 2 + + + + + + + + v m v m v m v m 36 37 32 31 35 34 33 17 18 19 7 osc in osc out v d v d sclk sdata latch exp0 exp1 v refsel v ref 21 22 ext ext a b 25 24 26 3 29 28 30 4 15 16 14 511 12106 fb a a 1 a 2 fil a fb b b 1 b 2 fil b fb c c 1 c 2 fil c fb d d 1 d 2 fil d 6.8 w 6.8 w 1000 pf 1000 pf
data sheet s14188ej1v0ds00 11 m m m m pd16879 timing chart (1) reset v d v d latch data sclk osc out start point wait (ff1) start point wait+ start point magnetize wait (ff2) enable out note 1 chopping exp 0, 1 pulse out pulse gate (ff3) pulse check note 2 (ff7) check sum note 3 sclk sdata 1st byte 13th byte (lsb) data is held at rising edge sclk d0 d1 d2 d3 d4 d5 d6 d7 initialization s1 s2 s3 s4 pulse 0 s5 ps s6 ps s7 release ps s8 s9 enable s10 release ps s11 s12 data error s13 normal data s14 s3 s1 s2 s2 s3 s4 s4 s4 s7 s8 s8 s9 s9 s10 s10 s11 s11 s12 s12 s13 s13 s14 h level fixation it reverts from the vd start after a ps release. l level fixation l level fixation stop from latch start from latch exp can be change in ps period too. output l level because error data s13 s11 s10 s9 s8 s2 s3 s4 s5 to s7 pulse is nothing because error data. pulse count is done in enable period too pulse is nothing because ps data pulse is nothing because pulse data is "0" notes 1. 2. 3. enable is set at the falling edge of ff1 when the level changes from low to high, and at the falling edge of ff2 when the level changes from high to low. ff7 is an output signal that is used to check for the presence or absence of a pulse in the serial data, is updated at the falling edge of latch and reset once at the rising edge of latch. if check sum is other than "00h", ff7 goes low, inhibiting pulse output, even if a pulse is generated. check sum output is updated at the falling edge of latch.
data sheet s14188ej1v0ds00 12 m m m m pd16879 timing chart (2) clk (pulse out) mob h bridge , 1ch output a b h bridge , 2ch output a b current direction: a1 to a2 current direction: a2 to a1 current direction: b2 to b1 current direction: b2 to b1 current direction: b1 to b2 (expanded view) (cw mode) cw mode ccw mode cw mode clk pulse out position no. h bridge 1ch output h bridge 2ch output cw cw cw cw cw cw ccw ccw ccw ccw 1 2 3 4 5 65 4 3 23 4 remarks 1. the current value of the actual wave is approximated to the value shown on the page 5. 2. the c1, c2, d1, and d2 pins of b channel correspond to the a1, a2, b1, and b2 pins of a channel. 3. the cw mode is set if the d6 bit of the fifth and ninth bytes of the data is 0. 4. the ccw mode is set if the d6 bit of the fifth and ninth bytes of the data is 1. note cw mode : position no is incremented. ccw mode: position no is decremented .
data sheet s14188ej1v0ds00 13 m m m m pd16879 standard characteristics curves p t vs. t a characteristics ambient temperature t a ( c) total power dissipation p t (w) 1.2 1.0 0.8 0.6 0.4 0.2 0 125 c/w ?0 0 20 40 60 80 100 120 i dd vs. v dd characteristics control circuit supply voltage v dd (v) v dd pin current i dd (ma) 7.0 6.0 5.0 4.0 3.0 2.0 0 t a = 25 c operating 123 4 5 6 1.0 i dd(reset) vs. v dd characteristics control circuit supply voltage v dd (v) v dd pin current (reset) i dd(reset) ( a) 350 300 250 200 150 100 0 t a = 25 c reset 123 4 5 6 m 50 v ih , v il vs. v dd characteristics control circuit supply voltage v dd (v) input voltage v ih , v il (v) 4.0 3.0 2.0 1.0 0 t a = 25 c 123 4 5 6 v il v ih i dd(ps) vs. v dd characteristics control circuit supply voltage v dd (v) v dd pin current (ps) i dd(ps1) , i dd(ps2) ( a) 600 500 400 300 200 100 0 t a = 25 c ps mode 123 4 5 6 m i dd(ps)2 i dd(ps)1 v ref vs. t a characteristics ambient temperature t a ( c) reference voltage v ref (ma) 254 253 252 251 250 249 245 v dd = 3.0 v v fil /2 02040 60 80 100 248 247 246 120 ?0
data sheet s14188ej1v0ds00 14 m m m m pd16879 i m vs. evr characteristics evr setting voltage evr (mv) sine wave peak output current i m (ma) 70 60 50 40 30 20 0 t a = 25 c, 70 w , 15 mv, v m = 5.4 v r s = 6.8 w , f osc = 72.58 khz 50 100 150 200 250 10 i m vs. v m characteristics output circuit supply voltage v m (v) sine wave peak output current i m (ma) 10 50 40 30 20 0 t a = 25 c, 70 w , 15 mh, r s = 6.8 w f osc = 72.58 khz, evr = 100 mv (10000) 246 8 12 10 i m vs. r s characteristics current sense resistor r s ( w ) sine wave peak output current i m (ma) 4 60 50 40 30 20 0 t a = 25 c, 70 w , 15 mh, v m = 5.4 v f osc = 72.58 khz, evr = 100 mv (10000) 6810 12 14 10 2 r on vs. v m characteristics output circuit supply voltage v m (v) h bridge on resistance r on ( w ) 4 8.0 6.0 4.0 2.0 0 t a = 25 c 6810 12 2 r on vs. t a characteristics ambient temperature t a ( c) h bridge on resistance r on ( w ) 20 8.0 6.0 4.0 2.0 ?0 0 40 60 80 100 120 0 v m = 4.0 v v m = 5.4 v v m = 8.0 v v m = 11 v
data sheet s14188ej1v0ds00 15 m m m m pd16879 i/f circuit data configuration (f clk = 4.5 mhz external clock input) input data consists of serial data (8 bits 13 bytes). input serial data with the lsb first, from the first byte to 13th byte. [1st byte] [2nd byte] bit data function setting bit data function setting d7 d7 d6 d6 d5 d5 d4 d4 d3 d3 d2 d2 d1 d1 d0 8 bit data input note first point wait first point wait 227.6 m s to 58.03 ms setting (1 to 255) d t = 227.6 m s d0 8 bit data input note first point magnetize wait first point magnetize wait 227.6 m s to 58.03 ms setting (1 to 255) d t = 227.6 m s note input other than 0 note input other than 0 [3rd byte] [4th byte] bit data function setting bit data function setting d7 1 or 0 exp1 z/l note 1 d7 1 or 0 power save off/on note 1 d6 1 or 0 exp0 z/l note 1 bit data ext a output ext b output d5 d6 note 5 enable note 2 enable note 2 d4 d5 note 5 rotation note 3 rotation note 3 d3 d4 note 5 pulse out pulse out d2 d3 note 5 ff7 ff7 d1 d2 note 5 ff3 ff3 d0 6 bit data input chopping frequency chopping frequency 35.71 khz to 225 khz setting (8 to 48) note 2 d1 note 5 checksum note 4 ff2 d0 note 5 chopping ff1 notes 1. z: high impedance/l: low level 2. 0 to 7 input: pwm and pulse out nothing 49 to 63 input: 225 khz fixed refer to 4 page notes 1. data 1: normal/data 0: power save 2. high: conducts/low: stops 3. high: reverse (ccw)/low: forward (cw) 4. high: normal data/low: error data 5. select one of d0 to d6 and input 1. if two or more of d0 to d6 are selected, they are positively ored for output.
data sheet s14188ej1v0ds00 16 m m m m pd16879 [5th byte] [6th byte] bit data function setting bit data function setting d7 1 or 0 enable aa ch on/off d7 d6 1 or 0 rotation aa ch ccw/cw d6 d5 0 not use not use d5 d4 d4 d3 d3 d2 d2 d1 d1 d0 5 bit data input a channel current set a channel current set note evr: 50 to 250 mv setting (11 to 31) d0 8 bit data input a channel pulse number a channel number of pulse in 1 v d 0 to 1020 pulses setting (0 to 255) d n = 4 pulses note note fixed to 50 mv if 0 to 10 input. refer to 4 page. note output pulse is nothing if data input 256, 512, and 768. [7th byte] [8th byte] bit data function setting bit data function setting d7 d7 d6 d6 d5 d5 d4 d4 d3 d3 d2 d2 d1 d1 d0 16 bti data low-order 8 bit data input a channel pulse cycle a channel pulse cycle 222 ns to 14.563 ms setting (1 to 65535) d t = 222 ns d0 16 bit data high-order 8 bit data input a channel pulse cycle a channel pulse cycle 222 ns to 14.563 ms setting (1 to 65535) d t = 222 ns note d0 bit of 7th byte is lsb, and d7 bit of 8th byte is msb. [9th byte] [10th byte] bit data function setting bit data function setting d7 1 or 0 enable bb ch on/off d7 d6 1 or 0 rotation bb ch ccw/cw d6 d5 0 not use not use d5 d4 d4 d3 d3 d2 d2 d1 d1 d0 5 bit data input b channel current set b channel current set note evr: 50 to 250 mv setting (11 to 31) d0 8 bit data input b channel pulse number b channel number of pulse in 1 v d 0 to 1020 pulses setting (0 to 255) d n = 4 pulses note note fixed to 50 mv if 0 to 10 input. refer to 4 page. note output pulse is nothing if data input 256, 512, and 768.
data sheet s14188ej1v0ds00 17 m m m m pd16879 [11th byte] [12th byte] bit data function setting bit data function setting d7 d7 d6 d6 d5 d5 d4 d4 d3 d3 d2 d2 d1 d1 d0 16 bit data low-order 8 bit data input b channel pulse cycle b channel pulse cycle 222 ns to 14.563 ms setting (1 to 65535) d t = 222 ns d0 16 bit data high-order 8 bit data input b channel pulse cycle b channel pulse cycle 222 ns to 14.563 ms setting (1 to 65535) d t = 222 ns note d0 bit of 11th byte is lsb, and d7 bit of 12th byte is msb. [13th byte] bit data function setting d7 d6 d5 d4 d3 d2 d1 d0 8 bit data input checksum checksum note note data is input so that the sum of the first through the 13th bytes is 00h.
data sheet s14188ej1v0ds00 18 m m m m pd16879 data configuration input data is composed of the serial data on 8 bits 13 bytes. input serial data with the lsb first, i.e., starting from the d0 bit (lsb) of the first byte. therefore, the d7 bit of the 13th byte is the most significant bit (msb). the establishment of the delay time to the output from the power supply injection, chopping frequency, output current, number of pulse, pulse cycle, and so on are possible with this product. the m pd16879 has an ext pin for monitoring the internal operations, the parameter to be monitored can be selected by serial data. the m pd16879 built in power save function. if set power save mode, consumption current decreased to about 1/10. input serial data during first point wait time (ff1: high level). this product uses separated external reference clock (f clk ). if they dont input f clk , this product cant operate normally. the establishment value which shows it in this document is at the time of f clk = 4.5 mhz. please be careful because establishment value is different in the case of one except for f clk = 4.5 mhz. detail of data configuration ho to input serial data is below. [1st byte] the 1st byte specifies the delay between data being read and data being output. this delay is called the first point wait time, and the motor can be driven from that point at which the first point wait time is 0. this time is counted at the rising edge of v d (or falling edge of v d ). the first point wait time can be set to 58.03 ms (when a 4.5 mhz clock input) and can be fine-tuned by means of 8-bit division (227.6 m s step: with 4.5 mhz clock). always input data other than 0 to this byte because the first point wait time is necessary for latching data. if 0 is input to this byte, data cannot be updated. transfer serial data during the first point wait time. table 3. 1st byte data configuration bitd7d6d5d4d3d2d1d0 datafirst point wait data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 00000000 prohibition msb lsb 00001001 about 2.05 ms 11111111 about 58.03 ms nn 1024/4.5 mhz
data sheet s14188ej1v0ds00 19 m m m m pd16879 [2nd byte] the 2nd byte specifies the delay between the first point wait time being cleared and the output pulse being generated. this time called the first point magnetize wait time, and the output pulse is generated from the point at which the start up wait time. the first point magnetize wait time is counted at the falling edge of the first point wait time. the first point magnetize wait time can be set to 58.03 ms (when a 4.5 mhz clock input) and can be fine-tuned by means of 8-bit division (227.6 m s step: with 4.5 mhz clock). always input data other than 0 to this byte because the first point magnetize wait time is necessary for latching data. if 0 is input to this byte, data cannot be updated. table 4. 2nd byte data configuration bitd7d6d5d4d3d2d1d0 datafirst point wait data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 00000000 prohibition msb lsb 00101001 about 9.33 ms 11111111 about 58.03 ms nn 1024/4.5 mhz [3rd byte] the 3rd byte sets the chopping frequency and external extension pins (exp0, exp1). the chopping frequency sets by bits d0 to d5. the exp pins goes low (current sink) when the input data is 0, and high (high-impedance state) when the input data is 1. pull this pin up to v dd for use. table 5. 3rd byte data configuration bitd7d6d5d4d3d2d1d0 data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 exp1 sets msb lsb exp0 sets chopping frequency sets d7: exp1 sets 1: high impedance 0: low level (current sink) d6: exp0 sets 1: high impedance 0: low level (current sink) the chopping frequency is set to 0 khz and to a value in the range of 35.71 khz to 225 khz (4.5 mhz clock input). refer to table 1 (4 page). [4th byte] the 4th byte selects a parameter to be output ext a and ext b pins (logic operation monitor pin). and, power save mode sets too. table 6. 4th byte data configuration bitd7d6d5d4d3d2d1d0 data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 power save sets test parameter select
data sheet s14188ej1v0ds00 20 m m m m pd16879 the test parameter is selected by bits d0 to d6. there are two ext pins. ext a indicates the operating status of a channel, and ext b indicates that of b channel. the relationship between each bit and each ext pin is as shown in table 7. table 7. output data of test parameter bit data ext a ext b d6 0 or 1 enable a enable b d5 0 or 1 rotation a rotation b d4 0 or 1 pulseout a pulseout b d3 0 or 1 ff7 a ff7 b d2 0 or 1 ff3 a ff3 b d1 0 or 1 checksum ff2 d0 0 or 1 chopping ff1 if two or more signals that output signals to ext a and ext b are selected, they are positively ored for output. the meanings of the symbols listed in table 7 are as follows: enable : output setting (high level: conducts/low level: stops) rotation : rotation setting (high level: reverse (ccw)/low level: forward (cw)) pulse out : output pulse signal ff7 : presence/absence of pulse in latch cycle (outputs h level if output pulse information exists in serial data.) ff3 : pulse gate (output while pulse exists) ff2 : outputs high level during first point wait time + first point magnetize wait time ff1 : outputs high level during first point wait time checksum : checksum output (high level: when normal data is transmitted/low level: when abnormal data is transmitted) chopping : chopping wave output power save mode sets by d7 bit. d7 bit data is 1: normal mode d7 bit data in 0: power save mode when power save mode is selected, circuit consumption current can be reduced. detail of power save function is refer to about power save mode (25 page). [5th byte] the 5th byte sets the enable, rotation, and output current of a channel. the enable sets by bit d7, the rotation sets by bit d6, and the output current sets by bits d0 to d4. bit d5 is fixed 0. bit d5 isnt use. table 8. 5th byte data configuration ( a a a a channel data) bitd7d6d5d4d3d2d1d0 data 0 or 1 0 or 1 0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 enable sets msb lsb rotation sets output current sets
data sheet s14188ej1v0ds00 21 m m m m pd16879 enable sets by d7 bit. d7 bit data is 0: output high impedance (but, internal counter increase) d7 bit data is 1: output conducts rotation sets by d6 bit. d6 bit data is 0: forward turn (cw mode) d6 bit data is 1: reverse turn (ccw mode) output current sets by d0 to d4 bits. the 250 mv (typical) voltage input from external source or internal reference voltage is internally doubled and input to a 5-bit d/a converter. by dividing this voltage by 5-bit data, a current setting reference voltage can be set inside the ic within the range of 100 to 500 mv, in units of 20 mv. if external source is used, the v refsel pin connects v dd pin. if internal reference voltage is used, the v refsel pin and v ref pin connect gnd pin. the 64 steps micro-step (setting reference voltage is maximum) control is possible. table 9. output current setting reference voltage data ( a a a a channel data) evr setting d4 d3 d2 d1 d0 fil pin voltage evr setting d4 d3 d2 d1 d0 fil pin voltage 50 mv 01011 100 mv 160 mv 10110 320 mv 60 mv 01100 120 mv 170 mv 10111 340 mv 70 mv 01101 140 mv 180 mv 11000 360 mv 80 mv 01110 160 mv 190 mv 11001 380 mv 90 mv 01111 180 mv 200 mv 11010 400 mv 100 mv 10000 200 mv 210 mv 11011 420 mv 110 mv 10001 220 mv 220 mv 11100 440 mv 120 mv 10010 240 mv 230 mv 11101 460 mv 130 mv 10011 260 mv 240 mv 11110 480 mv 140 mv 10100 280 mv 250 mv 11111 500 mv 150 mv 10101 300 mv remark if d0 to d4 bits input 00000 to 01010, evr value fixed 50 mv (fil pin voltage fixed 100 mv). fil pin (peak voltage) is output about double of evr setting value. [6th byte] the 6th byte sets pulse number during 1v d period of a channel. the pulse number setting 1020 pulses maximum. it is set by eight bits in terms of software. however, the actual circuit uses 10-bit counter with the low-order two bits fixed to 0. therefore, the number of pulses that is actually generated during fall edge of the first point wait time + first point magnetize wait time (ff2) cycle is the number of pulses input x 4. the number of pulses can be set in a range of 0 to 1020 and in units of four pulses. table 10. 6th byte data configuration ( a a a a channel data) bitd7d6d5d4d3d2d1d0 datapulse number/v d data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 00000000 0 msb lsb 00000001 4 11111111 1020 nn 4
data sheet s14188ej1v0ds00 22 m m m m pd16879 [7th, 8th byte] the 7th byte and 8th byte set the pulse cycle of the a channel. the pulse cycle is specified using 16 bits: bits d0 (least significant bit) to d7 of the 7th byte, and bits d0 to d7 (most significant bit) of the 8th byte. the pulse cycle can be set to a value in the range of 222 ns to 14.563 ms in units of 222 ns (with a 4.5 mhz clock). table 11 (a). 7th byte data configuration ( a a a a channel data) bitd7d6d5d4d3d2d1d0 data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 table 11 (b). 8th byte data configuration ( a a a a channel data) bitd7d6d5d4d3d2d1d0 data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 msb [9th byte] the 9th byte sets the enable, rotation, and output current of b channel. the enable sets by bit d7, the rotation sets by bit d6, and the output current sets by bits d0 to d4. bit d5 is fixed 0. bit d5 isnt use. table 12. 9th byte data configuration ( b b b b channel data) bitd7d6d5d4d3d2d1d0 data 0 or 1 0 or 1 0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 enable sets msb lsb rotation sets output current sets enable sets by d7 bit. d7 bit data is 0: output high impedance (but, internal counter increase) d7 bit data is 1: output conducts rotation sets by d6 bit. d6 bit data is 0: forward turn (cw mode) d6 bit data is 1: reverse turn (ccw mode) output current sets by d0 to d4 bits. the 250 mv (typical) voltage input from external source or internal reference voltage is internally doubled and input to a 5-bit d/a converter. by dividing this voltage by 5-bit data, a current setting reference voltage can be set inside the ic within the range of 100 to 500 mv, in units of 20 mv. if external source is used, the v refsel pin connects v dd pin. if internal reference voltage is used, the v refsel pin and v ref pin connect gnd pin. the 64 steps micro-step (setting reference voltage is maximum) control is possible. lsb
data sheet s14188ej1v0ds00 23 m m m m pd16879 table 13. output current setting reference voltage data ( b b b b channel data) evr setting d4 d3 d2 d1 d0 fil pin voltage evr setting d4 d3 d2 d1 d0 fil pin voltage 50 mv 01011 100 mv 160 mv 10110 320 mv 60 mv 01100 120 mv 170 mv 10111 340 mv 70 mv 01101 140 mv 180 mv 11000 360 mv 80 mv 01110 160 mv 190 mv 11001 380 mv 90 mv 01111 180 mv 200 mv 11010 400 mv 100 mv 10000 200 mv 210 mv 11011 420 mv 110 mv 10001 220 mv 220 mv 11100 440 mv 120 mv 10010 240 mv 230 mv 11101 460 mv 130 mv 10011 260 mv 240 mv 11110 480 mv 140 mv 10100 280 mv 250 mv 11111 500 mv 150 mv 10101 300 mv remark if d0 to d4 bits input 00000 to 01010, evr value fixed 50 mv (fil pin voltage fixed 100 mv). fil pin (peak voltage) is output about double of evr setting value. [10th byte] the 10th byte sets pulse number during 1v d period of b channel. the pulse number setting 1020 pulses maximum. it is set by eight bits in terms of software. however, the actual circuit uses 10-bit counter with the low- order two bits fixed to 0. therefore, the number of pulses that is actually generated during fall edge of the first point wait time + first point magnetize wait time (ff2) cycle is the number of pulses input 4. the number of pulses can be set in a range of 0 to 1020 and in units of four pulses. table 14. 10th byte data configuration ( b b b b channel data) bitd7d6d5d4d3d2d1d0 datapulse number/v d data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 00000000 0 msb lsb 00101001 164 11111111 1020 nn 4
data sheet s14188ej1v0ds00 24 m m m m pd16879 [11th, 12th byte] the 11th byte and 12th byte set the pulse cycle of the b channel. the pulse cycle is specified using 16 bits: bits d0 (least significant bit) to d7 of the 7th byte, and bits d0 to d7 (most significant bit) of the 8th byte. the pulse cycle can be set to a value in the range of 222 ns to 14.563 ms in units of 222 ns (with a 4.5 mhz clock). table 15 (a). 11th byte data configuration ( b b b b channel data) bitd7d6d5d4d3d2d1d0 data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 table 15 (b). 12th byte data configuration ( b b b b channel data) bitd7d6d5d4d3d2d1d0 data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 msb [13th byte] the 13th byte is checksum data. please input the data that sum of the 1st byte to 13th byte is 0. when the sum is 0, the stepping operation continued. if the sum is not 0 because data transmission is abnormal, the stepping operation is inhibited and ext pin (at the checksum selecting) is held at low level. lsb
data sheet s14188ej1v0ds00 25 m m m m pd16879 about power save mode it is possible that circuit electric current is made small in the power saving (the following ps) mode. data maintenance just before the ps mode and the maintenance of the phase position are done in the ps mode. circuit consumption current in the ps mode becomes 300 m a (max.) at the time of the outside clock (osc in ) = 4.5 mhz, and becomes 100 m a (max.) at the time of the outside clock (osc in ) stopped. it can be reduced in less than 1/10 in normal mode. (how to be within ps mode) the establishment of the ps mode is done by a d7 bits of the 4th byte. please follow the following process when it is within ps mode. (1) normal operation (pulse number > 1, enable: conducts) (2-1) normal operation (pulse number = 0, enable: conducts) (2-2) normal operation (pulse number = 0, enable: stops) (3) please input ps data. (effective timing of ps mode) chopping movement stops at the latch falling timing which ps data are contained to. first point wait count and first point magnetize wait count stop at the next v d rising timing which ps data are contained to. ff1 is fixed on the high level, and ff2 is fixed on low level. enable becomes low level at the latch falling timing which ps data are contained to. and, the outside expansion circuit (exp terminal) works at the time of ps mode too. (ps mode release movement) chopping movement resumes at the latch falling timing which ps release data are contained to. first point wait count and first point magnetize wait count resume at the next v d rising timing which ps release data are contained to. enalbe becomes high level at the first ff1 falling timing which ps release data are contained to. (when enable data is high level)
data sheet s14188ej1v0ds00 26 m m m m pd16879 data update timing the serial data of this product is set and update at the following timing. table 16. update timing of the data (1) data data set update timing first point wait time latch falling edge next v d rising edge or, next v d falling edge first point magnetize wait time latch falling edge ff1 falling edge exp latch falling edge latch falling edge chopping latch falling edge latch falling edge power save latch falling edge refer to 25 page the timing at which data is to be update differ, as shown in table 17, depending on the enable status. table 17. update timing of the data (2) change of enable 1 ? 10 ? 11 ? 00 ? 0 pulse cycle ff2 ff2 ff2 - pulse number ff2 ff2 ff2 - rotation ff2 ff2 ff2 - enable ff2 ff1 ff2 - evr latch latch latch - pulse cycle, pulse number, rotation are update enable is update (at the change of enable: 0 to 1) output current (evr) is updated v d latch ff1 ff2 pulse out
data sheet s14188ej1v0ds00 27 m m m m pd16879 initialization the ic operation can be initialized as follows: (1) turns on v dd . (2) make reset input low level signal. in initial mode, the operating status of the ic is as shown in table 18. table 18. operations in initial mode item specification current consumption 100 m a osc input of external clock is inhibited. v d , v d input inhibited. ff1 to ff7 low level pulse out low level exp0, exp1 low level in the case of (1) above. previous value is retained in the case of (2) above. serial operation can be accessed after initialization in the case of (1) above. can be accessed after reset has gone high level in the case of (2) above. step pulse output is inhibited and ff7 is made low level if the following conditions are satisfied. (1) if the set number of pulses (6th/10th byte) is 0. (2) if the checksum value is other than 0. (3) if the first point wait time (ff1) is set to 1v d or longer. (4) if the first point wait time + first point magnetize wait time (ff2) is set to 1v d or longer. (5) if the first point wait time (ff1) is completed earlier than falling timing of latch. (6) if v d is not input.
data sheet s14188ej1v0ds00 28 m m m m pd16879 hints on correct use (1) with this product, input the data for first point wait time and first point magnetize wait time. because the serial data are set or updated by these wait times, if the first point wait time and first point magnetize wait time are not input, the data are not updated. (2) the first point wait time must be longer than latch. (3) if the falling of the ff2 is the same as the falling of the last output pulse, a count error occurs, and the ic may malfunction. (4) transmit the serial data during the first point wait time (ff1). if it is input at any other time, the data may not be transmitted correctly. (5) if the lgnd potential is undefined, the data may not be input correctly. keep the lgnd potential to the minimum level. it is recommended that lgnd and pgnd be divided for connection (single ground) to prevent the leakage of noise from the output circuit.
data sheet s14188ej1v0ds00 29 m m m m pd16879 package drawings 38 20 119 s s a f g e c d n p l j h i k b detail of lead end m m item b c i l m n 38-pin plastic ssop (7.62 mm (300)) a d e f g h j p millimeters 0.65 (t.p.) 0.65 max. 0.10 0.6 0.2 5.6 0.2 0.10 12.7 0.3 0.125 0.075 0.37 1.675 0.125 7.7 0.2 1.55 + 0.05 - 0.1 1.05 0.2 3 + 7 - 3 note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. k 0.2 + 0.1 - 0.05 p38gs-65-bgg-1
data sheet s14188ej1v0ds00 30 m m m m pd16879 recommended soldering conditions solder this product under the following recommended conditions. for soldering methods and conditions other than those recommended, consult nec. for details of the recommended soldering conditions, refer to information document semiconductor device mounting technology manual . soldering method soldering conditions recommended condition infrared reflow package peak temperature: 235c, time: 30 secs max. (210c min.); number of times: 3 times max.; number of day: none; flux: rosin-based flux with little chlorine content (chlorine: 0.2 wt%, ax.) is recommended ir35-00-3 vps package peak temperature: 215c, time: 40 secs max. (200c min.); number of times: 3 times max.; number of day: none; flux: rosin-based flux with little chlorine content (chlorine: 0.2 wt%, ax.) is recommended. vp15-00-3 wave soldering package peak temperature: 260c; time: 10 secs max.; preheating temperature: 120c max; number of times: once; flux: rosin-based flux with little chlorine content (chlorine: 0.2 wt%, ax.) is recommended. ws60-00-1 caution do not use two or more soldering methods in combination.
data sheet s14188ej1v0ds00 31 m m m m pd16879 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pd16879 m8e 00. 4 the information in this document is current as of may, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above).

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